LSI construction of complex digital logic circuit design provides a compact solution to circuit problems via the very high packing density available in this art. This is in large part attributable to the very high percentage of the total volume consumed in the interconnecting wiring and connecting plugs required in older more conventional designs utilizing external wiring between standard element chip packages.
However, the decision to use LSI custom chips commits the designer to a large initial investment in terms of tooling costs. Further, unless the production volume is to be very large, the amortization of the tooling costs may cause the cost of each circuit produced to exceed reasonable economical limits. These problems have given rise to chip designs of the "universal use" type. That is, chips which have standard cell active elements deployed thereon, but with the interconnections in the form of custom metallization patterns left for design by the user. These chips have generally been designed so that various individual components are "wired" through use of a custom metallization layer to form gates, amplifiers, flip-flops, etc. or a chip may consist entirely of standard gate flip-flop or other cells; to be interconnected by a custom metallization pattern. While these circuit chips go part way in solution of the problems set out above, they still leave the designer to face some serious shortcomings. Packing density in these "universal" units do not approach that available by use of custom design of the entire chip for a specific circuit. An excessive amount of chip space is restricted to the interconnect metallization and in the case of a chip utilizing standard cells of only one circuit type, it is necessary to provide off chip interconnections to standard cells of another type. This further restricts the designer because the off chip connections are limited by the limited number of pin connections to the outside because of the very small chip sizes. The designer, having successfully overcome these hurdles then finds that when be accomplishes conversion of these universal designs to custom designs for high volume production, very little of what he has done is usable and the correlation between designs is very low. There is a very large reduction in total size and external wiring complexity leading to questionable usefulness of the initial design work.
Studies of some prior art logic circuits which are of a modular type readily available to the industry show that these circuits may be economically implemented as a part of a larger standardized logic chip if the ratio of gates to flip-flops lies in the range from 2.0-2.5 to 1. The circuits which are identified in Table I, below, are of this type and fit within the range of gate to flip-flop ratios when those amplifiers included therein for the purpose of isolating sinks and sources are deleted. This can be legitimately done for the purposes of gate to flip-flop ratio analysis since when these standard circuits are combined on a single chip, there is no need for the buffering functions as there is when sources and loads must be assumed to be located off chip.
TABLE I __________________________________________________________________________ Circuit Publication Part No. Type Manufacturer Reference Pages __________________________________________________________________________ DM 54/ Shift National TTL Data 2-79 DM 74165, Register Semiconductor Book, 2-76 thru L 165A Corp. 2-81 MC 14015 Shift Motorola, Semiconductor 7-45 Register Inc. Data Library, thru Vol. 5, McMos 7-50 Integrated Circuits, 1975 MC 14017 Decade Motorola, Same as above 7-57 Counter/ Inc. thru Divider 7-62 MC14518*, Decade Motorola, Same as above 7-200 MC14520* Counter Inc. thru 7-204 CD4018AD Decade RCA RCA COS/MOS 99 CD4018AE Counter/ Integrated CD4018AF Divider Circuits Book CD4018AK (SSD-203c), 1975 CD4022AD Divide by RCA Same as above 119 CD4022AE 8 Counter/ CD4022AF Divider CD4022AK __________________________________________________________________________ *This part includes 3-input gates. In a standard chip implementation wher only 2-input gates are available, it would be necessary to redesign the gate logic in 2-input gate configuration.
While implementation of the above circuits on a single large scale integrated circuit chip would rapidly lead to limitations imposed by a shortage of input/output bonding pads if all inputs and outputs of these circuits were necessarily connected to off-chip circuits, in most cases these and similar custom circuits may be interconnected on the large scale chip avoiding this problem.
The circuits of Table I are meant to be illustrative of circuits having a gate to flip-flop count ratio of from 2.0 to 2.5 and certainly the custom circuits which might have that ratio are not limited to those of or similar to the circuits of Table I. We have implemented two custom circuits having 67 gates and 29 flip-flops and 62 gates and 27 flip-flops, respectively, (ratio of approximately 2.3 to 1 in each case) on the chip of the invention.